--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   23:31:54 10/09/2013
-- Design Name:   
-- Module Name:   C:/Users/Ling Chun Kai/Documents/NUS modules/CG3207/Lab/CG3207/div_subtractor_test.vhd
-- Project Name:  LAB2
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: div_sub_and_select
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY div_subtractor_test IS
END div_subtractor_test;
 
ARCHITECTURE behavior OF div_subtractor_test IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT div_sub_and_select
    PORT(
         times1 : IN  std_logic_vector(34 downto 0);
         times2 : IN  std_logic_vector(34 downto 0);
         times3 : IN  std_logic_vector(34 downto 0);
         feedback_in : IN  std_logic_vector(31 downto 0);
         is_signed : IN  std_logic;
         out_diff : OUT  std_logic_vector(31 downto 0);
         quotient_digit : OUT  std_logic_vector(1 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal times1 : std_logic_vector(34 downto 0) := (others => '0');
   signal times2 : std_logic_vector(34 downto 0) := (others => '0');
   signal times3 : std_logic_vector(34 downto 0) := (others => '0');
   signal feedback_in : std_logic_vector(31 downto 0) := (others => '0');
   signal is_signed : std_logic := '0';

 	--Outputs
   signal out_diff : std_logic_vector(31 downto 0);
   signal quotient_digit : std_logic_vector(1 downto 0);
   -- No clocks detected in port list. Replace <clock> below with 
   -- appropriate port name 
 
   
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: div_sub_and_select PORT MAP (
          times1 => times1,
          times2 => times2,
          times3 => times3,
          feedback_in => feedback_in,
          is_signed => is_signed,
          out_diff => out_diff,
          quotient_digit => quotient_digit
        );

   
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	

		times1 <= "00"&x"f000beaf";
		times2 <= "01"&x"e0017d5e";
		times3 <= "10"&x"d0023c0d";
		
		feedback_in <= x"00000001";
		is_signed <= '0';
		
		wait;
		
      -- insert stimulus here 

      wait;
   end process;

END;
